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1 features applications description trf3710 slws199a ? august 2007 ? revised february 2008 www.ti.com iq demodulator 2 frequency range: 1.7 ghz to 2 ghz integrated baseband programmable-gain amplifier on-chip programmable baseband filter high cascaded ip3: 21 dbm at 1.9 ghz high ip2: 60 dbm at 1.9 ghz hardware and software power down 3-wire serial programmable interface single supply: 4.5-v to 5.5-v operation wireless infrastructure: ? wcdma ? cdma wireless local loop high-linearity direct downconversion receiver the trf3710 is a highly linear and integrated direct-conversion quadrature demodulator optimized for third-generation (3g) wireless infrastructure. the trf3710 integrates balanced i and q mixers, lo buffers, and phase splitters to convert an rf signal directly to i and q baseband. the on-chip programmable-gain amplifiers allow adjustment of the output signal level without the need for external variable-gain (attenuator) devices. the trf3710 integrates programmable baseband low-pass filters that attenuate nearby interference, eliminating the need for an external baseband filter. housed in a 7-mm 7-mm qfn package, the trf3710 provides the smallest and most integrated receiver solution available for high-performance equipment. available device options (1) specified package package package ordering transport media, product temperature lead designator markings number quantity range trf3710irgzr tape and reel, 2500 trf3710 qfn-48 rgz ? 40 c to 85 c trf3710 trf3710irgzt tape and reel, 500 (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2007 ? 2008, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. gnddig vccdig chip_en vccmix ncnc nc nc nc mixinp mixinn vccmix 12 3 4 5 6 7 8 9 10 11 12 25 26 27 28 29 30 31 32 33 34 35 36 vccbbi agnd bbioutpbbioutn loip loin ncbbqoutp bbqoutn agnd vccbbq vcclo 13 14 15 16 17 18 19 20 21 22 23 24 37 38 39 40 41 42 43 44 45 46 47 48 nc nc nc mixqoutn nc nc rext vccbias gndbias voffq vcmq clock da ta strobe mixioutp mixioutn nc nc gain_b0 gain_b1 gain_b2 voffi vcmi to microcontroller to microcontroller trf3710 rfin 30 k w to adc i to adc q loin mixqoutp
functional block diagram trf3710 slws199a ? august 2007 ? revised february 2008 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 2 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): trf3710 www.ti.com decoupling requiredvccdig 2 vccmix 4 and 9 vccbias 21 vccbbq 25 vccbbi 36 vcclo 29 vccs gnds gnddig 1gndbias 22 agnd 26 agnd 35 power down ce 3 6 41 31 30 7 mixinp gain_b0 loip loin mixinn 4039 gain_b1gain_b2 90 0 dc offset cancel dc offset cancel pgapga outbuffer outbuffer pga fast gain control bbioutn data strobe bbqoutn bbioutpvoffi vcmq vcmivoffq bbqoutp 3347 46 27 3438 24 3723 28 spi clock 48 gnddig vccdig chip_en vccmix ncnc nc nc nc mixinp mixinn vccmix 12 3 4 5 6 7 8 9 10 11 12 25 26 27 28 29 30 31 32 33 34 35 36 vccbbi agnd bbioutpbbioutn loip loin ncbbqoutp bbqoutn agnd vccbbq vcclo 13 14 15 16 17 18 19 20 21 22 23 24 37 38 39 40 41 42 43 44 45 46 47 48 nc nc nc mixqoutp mixqoutn nc nc rext vccbias gndbias voffq vcmq clock data strobe mixioutp mixioutn nc nc gain_b0 gain_b1 gain_b2 voffi vcmi rgz package (top view) trf3710
thermal characteristics trf3710 slws199a ? august 2007 ? revised february 2008 terminal functions terminal i/o description name no. agnd 26, 35 analog ground; grounds can be tied together. bbioutn 33 o baseband i output: negative terminal bbioutp 34 o baseband i output: positive terminal bbqoutn 27 o baseband q output: negative terminal bbqoutp 28 o baseband q output: positive terminal chip_en 3 i chip enable; enabled = logic level 1, disabled = logic level 0 clock 48 i spi clock input spi data input (programming data for baseband filter frequency setting, pga gain settings, and dc data 47 i offset calibration). gain_b0 41 i pga fast-gain control bit 0 gain_b1 40 i pga fast-gain control bit 1 gain_b2 39 i pga fast-gain control bit 2 gndbias 22 bias-block ground. grounds can be tied together. gnddig 1 digital ground. grounds can be tied together. loin 30 i local oscillator input: negative terminal loip 31 i local oscillator input: positive terminal mixer input: negative terminal, connected to external balanced-to-unbalanced (balun) transformer; mixinn 7 i balun type is frequency-specific. mixioutn 44 o mixer i output: negative terminal (test pin). nc for normal operation mixioutp 45 o mixer i output: positive terminal (test pin). nc for normal operation mixinp 6 i mixer input: positive terminal, connected to external balun; balun type is frequency-specific. mixqoutn 17 o mixer q output: negative terminal (test pin). nc for normal operation mixqoutp 16 o mixer q output: positive terminal (test pin). nc for normal operation rext 20 o reference-bias external resistor: 30 k ? ; used to set the bias of internal circuits of chip strobe 46 i spi enable (latches data into spi after final clock pulse. logic level = 1. vccbbq 25 baseband q-chain power supply, 4.5 v to 5.5 v. decoupled from other sources vccbias 21 bias-block power supply, 4.5 v to 5.5 v. decoupled from other sources vccdig 2 digital power supply, 4.5 v to 5.5 v. decoupled from other sources vcclo 29 local oscillator power supply, 4.5 v to 5.5 v. decoupled from other sources vccmix 4, 9 mixer power supply, 4.5 v to 5.5 v. decoupled from other sources vcmq 24 i baseband q-chain input common mode, nominally 1.5 v voffq 23 i q-chain analog-offset correction input, 0 v to 3 v. vccbbi 36 baseband i power supply, 4.5 v to 5.5 v. decoupled from other sources vcmi 37 i baseband i chain input common mode, nominally 1.5 v voffi 38 i i-chain analog-offset correction input, 0 v to 3 v over operating free-air temperature range (unless otherwise noted) parameter (1) test conditions min typ max unit soldered slug, no airflow 26 r q ja soldered slug, 200-lfm (1,016 m/s) airflow 20.1 thermal derating, junction-to-ambient c/w soldered slug, 400-lfm (2,032 m/s) airflow 17.4 r q ja (2) 7-mm 7-mm, 48-pin pdfp 25 r q jb thermal derating, junction-to-board 7-mm 7-mm, 48-pin pdfp 12 c/w (1) determined using jedec standard jesd-51 with high-k board (2) 16 layers, high-k board copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 3 product folder link(s): trf3710 www.ti.com
absolute maximum ratings (1) recommended operating conditions electrical characteristics trf3710 slws199a ? august 2007 ? revised february 2008 over operating free-air temperature range (unless otherwise noted) value unit supply voltage range (2) ? 0.3 to 5.5 v digital i/o voltage range ? 0.3 to v cc + 0.5 v t j operating virtual junction temperature range ? 40 to 150 c t a operating ambient temperature range ? 40 to 85 c t stg storage temperature range ? 65 to 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. over operating free-air temperature range (unless otherwise noted) min nom max unit v cc power supply voltage 4.5 5 5.5 v power supply voltage ripple 940 m v pp t a operating ambient temperature range ? 40 85 c t j operating virtual junction temperature range ? 40 150 c power supply = 5 v, lo = 0 dbm at 25 c (unless otherwise noted) parameter test conditions (1) min typ max unit dc parameters i cc total supply current 360 ma power-down current 5 ma iq demodulator and baseband section f rf frequency range 1700 2000 mhz g minbb minimum gain 20 db g maxbb maximum gain 43 45 db gain range 22 24 db gain step 1 (2) db nf bb noise figure gain setting = 15 13.5 14.5 db iip3 bb third-order input intercept gain setting = 15 (3) (4) 21 dbm point oip3 bb output third intercept point gain setting = 15; two tones, 1 v pp each (5) 32 dbvrms oip1 bb output compression point one tone (6) 3 dbvrms iip2 bb second-order input intercept gain setting = 15 (7) 60 dbm point baseband low-pass filter cutoff f lpf 1-db point (8) 0.615 1.92 mhz frequency (1) balun used for measurements: band 1: 1700-mhz balun = murata ldb211g8005c-001; band 2: 1800- to 1900-mhz balun = murata ldb211g9005c-001 (2) between two consecutive gain settings (3) two cw tones of ? 30 dbm at 900-khz and 1.7-mhz offset (baseband filter 1-db cutoff frequency of minimum lpf). (4) two cw tones of ? 30 dbm at 2.7-mhz and 5.9-mhz offset (baseband filter 1-db cutoff frequency of maximum lpf). (5) two cw tones at an offset from lo frequency smaller than the baseband filter cutoff frequency. (6) single cw tone at an offset from lo smaller than the baseband filter cutoff frequency. (7) two tones at f rf1 = f lo 900 khz and f rf2 = f lo 1 mhz; im 2 product measured at 100-khz output frequency (for minimum baseband filter 1-db cutoff frequency). the two tones are at f rf1 = f lo 2.7 mhz and f rf2 = f lo 2.8 mhz, and the im 2 product measured at 100-khz output frequency (for maximum baseband filter 1-db cutoff frequency). (8) baseband low-pass filter 1-db cutoff frequency is programmable through spi between minimum and maximum values. 4 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): trf3710 www.ti.com
trf3710 slws199a ? august 2007 ? revised february 2008 electrical characteristics (continued) power supply = 5 v, lo = 0 dbm at 25 c (unless otherwise noted) parameter test conditions (1) min typ max unit 615 khz 1 900 khz 10 baseband relative attenuation at minimum lpf cutoff 1.7 mhz 50 db frequency (9) 5 mhz 60 20 mhz 100 1.92 mhz 1 baseband relative attenuation 2.7 mhz 10 at maximum lpf cutoff db 5 mhz 50 frequency (9) 20 mhz 100 baseband filter phase linearity rms phase deviation from linear phase (10) 1.8 degrees baseband filter amplitude see (10) 0.5 db ripple sideband suppression 35 db output load impedance parallel resistance 1 k ? parallel capacitance 20 pf v cm output common mode measured at i and q channel baseband outputs 0.7 1.5 4 v local oscillator parameters local oscillator frequency 1700 2000 mhz lo input level 0 dbm lo leakage at mixinn/p ? 58 dbm digital interface v ih high-level input voltage 2 5 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage 0.8 v cc v v ol low-level output voltage 0.2 v cc v (9) attenuation relative to passband gain (10) across-filter passband: 615 khz (minimum baseband filter cutoff frequency) and 1.92 mhz (maximum baseband filter cutoff frequency). copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 5 product folder link(s): trf3710 www.ti.com
timing requirements trf3710 slws199a ? august 2007 ? revised february 2008 power supply = 5 v, lo = 0 dbm at 25 c (unless otherwise noted) parameter test conditions min typ max unit t (clk) clock period 50 ns t su1 setup time, data 10 ns t h hold time, data 10 ns t w pulse width, strobe 20 ns t su2 setup time, strobe 10 ns figure 1. serial programming timing 6 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): trf3710 www.ti.com db1 address bit 2 db2 cmd bit 3 db3 cmd bit 4 db29 cmd bit 30 db30 cmd bit 31 db31 (msb) cmd bit 32 db0 (lsb) address bit 1 clock data strobe first clock pulse t su1 t su2 t h t w t (clk)
typical characteristics trf3710 slws199a ? august 2007 ? revised february 2008 v cc = 5 v, t a = 25 c, 1950 mhz, gain setting = 24 (unless otherwise stated). (cdma = bbfreq = 90, wcdma = bbfreq = 7) gain vs frequency gain vs gain state figure 2. figure 3. iip 3 vs frequency iip 3 vs frequency figure 4. figure 5. iip 3 vs frequency iip 3 vs frequency figure 6. figure 7. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 7 product folder link(s): trf3710 10 12 14 16 18 20 22 24 26 28 30 1690 1700 1710 1720 1730 1740 1750 1760 1770 1780 1790 iip C dbm 3 f C frequency C mhz cdma C40c 85c 25c 10 12 14 16 18 20 22 24 26 28 30 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000 iip C dbm 3 4.5 v 5 v 5.5 v f C frequency C mhz wcdma 10 12 14 16 18 20 22 24 26 28 30 1690 1700 1710 1720 1730 1740 1750 1760 1770 1780 1790 iip C dbm 3 85c 25c C40c f C frequency C mhz wcdma 10 12 14 16 18 20 22 24 26 28 30 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000 f C frequency C mhz iip C dbm 3 C40c 25c 85c wcdma www.ti.com 41.5 42 42.5 43 43.5 44 1820 1840 1860 1880 1900 1940 1960 1980 2000 gain C db 85c C40c f C frequency C mhz 25c cdma 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 0 2 4 6 8 10 12 14 16 18 24 gain state gain C db 25c 85c C40c cdma 20 22
trf3710 slws199a ? august 2007 ? revised february 2008 typical characteristics (continued) v cc = 5 v, t a = 25 c, 1950 mhz, gain setting = 24 (unless otherwise stated). (cdma = bbfreq = 90, wcdma = bbfreq = 7) iip 2 vs frequency iip 2 vs frequency figure 8. figure 9. iip 2 vs frequency iip 2 vs frequency figure 10. figure 11. oip 3 vs frequency oip 3 vs frequency figure 12. figure 13. 8 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): trf3710 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000 iip C dbm 2 4.5 v 5 v 5.5 v f C frequency C mhz wcdma 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 1690 1700 1710 1720 1730 1740 1750 1760 1770 1780 1790 iip C dbm 2 25c C40c 85c f C frequency C mhz wcdma 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 1690 1700 1710 1720 1730 1740 1750 1760 1770 1780 1790 iip C dbm 2 85c 25c C40c f C frequency C mhz wcdma 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000 f C frequency C mhz iip C dbm 2 C40c 25c 85c wcdma 20 22 24 26 28 30 32 34 36 38 40 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000 oip C dbv rms 3 f C frequency C mhz C40c 85c 25c cdma 20 22 24 26 28 30 32 34 36 38 40 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000 f C frequency C mhz oip C dbvrms 3 C40c 85c 25c wcdma www.ti.com
trf3710 slws199a ? august 2007 ? revised february 2008 typical characteristics (continued) v cc = 5 v, t a = 25 c, 1950 mhz, gain setting = 24 (unless otherwise stated). (cdma = bbfreq = 90, wcdma = bbfreq = 7) oip 3 vs gain state oip 3 vs gain state figure 14. figure 15. oip 3 vs lo power iip 3 vs lo power figure 16. figure 17. iip 2 vs lo power gain error vs gain state figure 18. figure 19. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 9 product folder link(s): trf3710 20 22 24 26 28 30 32 34 36 38 40 0 5 10 15 20 25 30 gain state oip C dbvrms 3 C40c 85c 25c wcdma 20 22 24 26 28 30 32 34 36 38 40 0 5 10 15 20 25 30 gain state oip C dbvrms 3 C40c 85c 25c cdma 15 20 25 30 35 40 45 C6 C4 C2 0 2 4 6 lo power C dbm oip C dbv rms 3 wcdma 5 10 15 20 25 30 35 C6 C4 C2 0 2 4 6 lo power C dbm iip C dbm 3 wcdma 15 20 25 30 35 40 45 50 55 60 65 70 75 C6 C4 C2 0 2 4 6 lo power C dbm iip C dbm 2 wcdma 0 5 10 15 20 25 gain state gain error C db 1850 mhz C0.002 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 www.ti.com
trf3710 slws199a ? august 2007 ? revised february 2008 typical characteristics (continued) v cc = 5 v, t a = 25 c, 1950 mhz, gain setting = 24 (unless otherwise stated). (cdma = bbfreq = 90, wcdma = bbfreq = 7) gain vs baseband frequency gain vs baseband frequency figure 20. figure 21. corner frequency vs bb ? frequency setting integrated nf vs gain state figure 22. figure 23. integrated nf vs gain state figure 24. 10 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): trf3710 C80 C60 C40 C20 0 20 40 60 0.01 0.1 1 10 100 baseband frequency C mhz gain C db filter gain shape 25c, (1.92 mhz) bb filter setting = 7 filter gain shape 25c, (615 khz) bb filter setting = 90 41.6 41.7 41.8 41.9 42 42.1 42.2 42.3 42.4 42.5 42.6 0.01 0.1 1 10 baseband frequency - mhz gain C db filter gain shape 25c, (1.92 mhz) bb filter setting = 7 filter gain shape 25c, (615 khz) bb filter setting = 90 0 5 10 15 20 25 gain state noise figure C db cdma mode 1950 mhz 25 c 10 15 20 25 30 5 v 4.5 v 5.5 v 0 0.5 1 1.5 2 2.5 3 0 16 32 48 64 80 96 112 128 bb C frequency setting f C frequency C mhz 1 db5 v 25c 1950 mhz www.ti.com 0 5 10 15 20 25 gain state noise figure C db cdma mode 1950 mhz 5 v 10 15 20 25 30 25 c C40 c 85 c
typical characteristics histogram plots trf3710 slws199a ? august 2007 ? revised february 2008 conversion gain distribution iip 3 distribution figure 25. figure 26. iip 2 distribution oip 3 distribution figure 27. figure 28. nf distribution figure 29. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 11 product folder link(s): trf3710 www.ti.com 0 20 40 60 80 iip3 C dbm distribution C % cdma 18.5 19 19.5 20 20.5 21 21.5 22 22.5 23 0 10 20 30 40 50 60 42.6 42.8 43 43.2 43.4 43.6 43.8 gain C db distribution C % 0 5 10 15 20 25 30 35 oip C dbvrms 3 distribution C % cdma wcdma 29 30 31 32 33 34 35 36 0 10 20 30 40 iip C dbm 2 distribution C % cdma wcdma 54 58 62 66 70 74 78 82 0 10 20 30 40 50 60 70 12.75 13 13.25 13.75 14 14.25 nf C db distribution C % 13.5
serial interface programming registers definition trf3710 slws199a ? august 2007 ? revised february 2008 the trf3710 features a 3-wire serial programming interface (spi) that controls an internal 32-bit shift register. there are a total of three signals that must be applied: clock (pin 48), serial data (pin 47), and strobe (pin 46). data (db0 ? db31) is loaded lsb-first and is read on the rising edge of the clock. strobe is asynchronous to clock, and at its rising edge, the data in the shift register are loaded onto the selected internal register. the first two bits (db0 ? db1) are the address to select the available internal registers. figure 30 shows the serial interface timing for the trf3710. parameter test conditions min typ max unit t (clk) clock period 50 ns t su1 setup time, data 10 ns t h hold time, data 10 ns t w pulse width, strobe 20 ns t su2 setup time, strobe 10 ns figure 30. serial interface timing 12 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): trf3710 www.ti.com db1 address bit 2 db2 cmd bit 3 db3 cmd bit 4 db29 cmd bit 30 db30 cmd bit 31 db31 (msb) cmd bit 32 db0 (lsb) address bit 1 clock data strobe first clock pulse t su1 t su2 t h t w t (clk)
register 0 trf3710 slws199a ? august 2007 ? revised february 2008 pwd bb pwd pwd pwd pwd pwd pwd ana freq register address test output rsvd dig cal baseband gain setting mixer lo buff filter cal cutoff buff buff block block set bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit12 bit13 bit14 bit15 dc detector cal baseband freq cutoff settings cont. rsvd rsvd spare spare bandwidth reset bit16 bit17 bit18 bit19 bit20 bit21 bit22 bit23 bit24 bit25 bit26 bit27 bit28 bit29 bit30 bit31 figure 31. register 0 map table 1. register 0: device setup reset register 0 name working description value bit0 addr_0 0 address bits bit1 addr_1 0 bit2 pwd_mix 0 mixer power down (off = 1) bit3 pwd_lo 0 lo buffer power down (off = 1) bit4 pwd_buf1 1 test buffer power down (off = 1) bit5 pwd_filt 0 baseband filter power down (off = 1) bit6 pwd_buf2 0 output buffer power down (off = 1) bit7 reserved 0 bit8 pwd_dc_off_dig 1 digital calibration blocks power down (off = 1) bit9 pwd_dc_off_ana 1 analog calibration blocks power down (off = 1) bit10 bbgain_0 1 sets baseband gain: the default power-on bbgain setting = 15 (corresponding to a typical gain of 34 db). there are 25 gain settings (0 to 24) in 1-db increments. for a bit11 bbgain_1 1 desired device gain, the bbgain setting is determined by the following equation: bit12 bbgain_2 1 bbgain setting = 24 ? [(typical device gain at bbgain = 24) ? (desired device bit13 bbgain_3 1 gain)]. for example, for a desired device gain of 27 db, the bbgain setting would be 24 ? (43 ? 27) = 8, which is bits 14 ? 10 <0 1000>. bit14 bbgain_4 0 bit15 bbfreq_0 1 bit16 bbfreq_1 0 sets bb frequency cutoff; default = 85. example: for cdma, the corner frequency is bit17 bbfreq_2 1 615 khz. see the 1-db corner frequency vs. frequency setting plot figure 22 to bit18 bbfreq_3 0 determine the setting, which is 90. then set bit 15 through bit 21 to <101 1010>, bit19 bbfreq_4 1 which corresponds to 90. bit20 bbfreq_5 0 bit21 bbfreq_6 1 bit22 reserved 1 bit23 reserved 0 bit24 en_flt_b0 0 dc detector bandwidth bit25 en_flt_b1 0 bit26 reserved 0 bit27 internal use only 0 bit28 internal use only 0 bit29 cal_reset 0 reset the internal calibration logic when = 1. bit30 spare0 0 bit31 spare1 0 copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 13 product folder link(s): trf3710 www.ti.com
trf3710 slws199a ? august 2007 ? revised february 2008 baseband pga gain: bbgain_[4:0] (b[14:10]) sets the gain of the baseband programmable gain amplifier. the acceptable values are from <0 0000> to <1 1000>. (see the gain control section for more information.) baseband filter cutoff frequency: bbfreq_[6:0] (b[21:15]) controls the baseband 1-db cutoff frequency. an all-0s word sets the filter to its maximum cutoff frequency, whereas an all-1s word corresponds to minimum filter bandwidth. en_flt_b[0:1]: these bits control the bandwidth of the detector used to measure the dc offset during the automatic calibration. there is an rc filter in front of the detector that can be fully bypassed. en_flt_b0 controls the resistor (bypass = 1), while en_flt_b1 controls the capacitor (bypass = 1). the typical 3-db cutoff frequencies of the detector bandwidth are summarized in table 2 (see the application information section for more detail on the dc offset calibration and the detector bandwidth). table 2. typical cutoff frequencies typical 3-db cutoff en_flt_b1 en_flt_b0 notes frequency x 0 10 mhz maximum bandwidth; bypass r, c 0 1 10 khz enable r 1 1 1 khz minimum bandwidth; enable r, c 14 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): trf3710 www.ti.com
register 1 trf3710 slws199a ? august 2007 ? revised february 2008 enable register address autocal dac bits to be set during manual cal i/q autocal bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit12 bit13 bit14 bit15 dc offset digital dc offset digital bin division ratio for clock cal clk dac bits cont cal. resolution cal. resolution internal osc freq trimming search divider select for i channel for q channel bit16 bit17 bit18 bit19 bit20 bit21 bit22 bit23 bit24 bit25 bit26 bit27 bit28 bit29 bit30 bit31 figure 32. register 1 map table 3. register 1: device setup reset register 1 name working description value bit0 addr_0 1 address bits bit1 addr_1 0 bit2 auto_cal 1 auto dc offset correction when = 1; otherwise manual bit3 en_autocal 0 autocalibration begins when bit = 1. this bit is reset after calibration completes. bit4 idac_bit0 0 bit5 idac_bit1 0 bit6 idac_bit2 0 bit7 idac_bit3 0 bit8 idac_bit4 0 bit9 idac_bit5 0 bit10 idac_bit6 0 bit11 idac_bit7 1 dac bits to be set during manual cal i/q bit12 qdac_bit0 0 bit13 qdac_bit1 0 bit14 qdac_bit2 0 bit15 qdac_bit3 0 bit16 qdac_bit4 0 bit17 qdac_bit5 0 bit18 qdac_bit6 0 bit19 qdac_bit7 1 bit20 idet_b0 1 set the dc offset digital calibration resolution for i channel. bit21 idet_b1 1 bit22 qdet_b0 1 set the dc offset digital calibration resolution for q channel. bit23 qdet_b1 1 bit24 bin search 1 set to 1 for autocalibration; set to 0 for manual control. bit25 clk_div_ratio0 0 dc offset autocalibration clock divider: bit26 clk_div_ratio1 0 division ratios = 1, 8, 16, 128, 256, 1024, 2048, 16,684 bit27 clk_div_ratio2 0 bit28 cal_clk_sel 1 select internal oscillator when 1; select spi clock when 0. bit29 osc_trim0 1 internal oscillator frequency trimming bit30 osc_trim1 1 000 300 khz 111 1.8 mhz bit31 osc_trim2 0 copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 15 product folder link(s): trf3710 www.ti.com
trf3710 slws199a ? august 2007 ? revised february 2008 auto_cal (bit2): when 1, the dc offset autocalibration is selected. en_autocal (bit3): setting this bit to 1 starts the dc offset autocalibration. at the end of the calibration, the bit is reset to 0 (see the application information section for more details on dc offset correction). idet_b[1:0], qdet_b[1:0]: these bits control the maximum output dc voltage of the dc-offset correction dac (i and q channels). clk_div_ratio[2:0]: frequency divider for the calibration clock. the incoming clock (either the serial interface clock or the internal oscillator) divided by the divider ratio set by bits 25 ? 27, generates the reference clock used during the autocalibration. cal_clk_sel: selects the internal oscillator or the external spi clock as calibration clock osc_trim[2:0]: bits 29 ? 31 control the internal oscillator frequency. 16 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): trf3710 www.ti.com
application information gain control automated dc offset calibration trf3710 slws199a ? august 2007 ? revised february 2008 the trf3710 integrates a baseband programmable-gain amplifier (pga) that provides 24 db of gain range with 1-db steps. the pga gain is controlled through spi by a 5-bit word (register 0, bits 10 ? 14). alternatively, the pga can be programmed by a combination of 5 bits programmed through the spi and three parallel external bits (pins gain_b2, gain_b1, gain_b0). the parallel bits allow a fast gain change (0 db to 7 db by 1-db steps) without the need to reprogram the spi registers. the pga gain control word ( bbgain[0:4]) can be programmed to a setting between 0 and 24. this word is the sum of the spi programmed gain (register 0, bits 10 ? 14) and the parallel external 3 bits as shown in figure 33 . setting the pga gain setting above 24 is not valid. typical applications set the pga gain to 15, which allows room to adjust the pga gain up or down to maintain desired output signal to the analog-to-digital converter over all conditions. figure 33. pga gain control word for example, if a pga gain setting of 20 db is desired, then the spi can be programmed directly to 20. alternatively, the spi gain register can be programmed to 15 and the parallel external bits set to 101 (binary), corresponding to an additional 5 db. the trf3710 provides an automatic calibration procedure for adjusting the dc offset in the baseband i/q paths. the digital dc offset correction is engaged by setting the pwd_dc_off_dig (register 0, bit 8) to 0 and the pwd_dc_off_ana (register 0, bit 9) to 1. the internal calibration requires a clock in order to function. trf3710 can use the internal relaxation oscillator or the external spi clock. using the internal oscillator is the preferred method. selecte the internal oscillator by setting the cal_sel_clk (register 1, bit 28) to 1. the internal oscillator frequency is set through the osc_trim bits (register 1, bits 29 ? 31). the frequency of the oscillator is detailed in table 4 . table 4. internal oscillator frequency control osc_trim2 osc_trim1 osc_trim0 frequency 0 0 0 300 khz 0 0 1 500 khz 0 1 0 700 khz 0 1 1 900 khz 1 0 0 1.1 mhz 1 0 1 1.3 mhz 1 1 0 1.5 mhz 1 1 1 1.8 mhz the default setting of these registers corresponds to 900-khz oscillator frequency; this setting is sufficient for autocalibration and does not need to be modified. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 17 product folder link(s): trf3710 www.ti.com register 0, bits 0C4 bbgain[0:4] fgain[0:2] + from spi to pga from external pins
(1) trf3710 slws199a ? august 2007 ? revised february 2008 the internal dc offset correction dacs output full scale range is programmable ( idet_b[0:1] and qdet_b[0:1], register 1, bits 20 ? 23). the range is shown in table 5 . table 5. dc offset correction dac programmable range i(q)det_b1 i(q)det_b0 full scale 0 0 10 mv 0 1 20 mv 1 0 30 mv 1 1 40 mv the maximum dc offset correction range can be calculating by multiplying the values in table 5 by the baseband pga gain. the lsb of the digital correction depends on the programmed maximum correction range. for optimum resolution and best correction, the dc offset dac range should be set to 10 mv for both the i and q channels with the pga gain set for the nominal condition. the output of the dc-offset-correction dac is affected by a change in the pga gain, but if the initial calibration yields optimum results, then the adjustment of the pga gain during normal operation does not significantly impair the dc offset balance. for example, if the optimized calibration yields a dc offset balance of 2 mv at a gain setting of 17, then the dc offset maintains less than 10-mv balance as the gain is adjusted 7 db. the dc offset correction dacs are programmed from the internal registers when the auto_cal bit (register 1, bit 2) is set to 1. at start-up, the internal registers are loaded at half-scale, corresponding to a decimal value of 128. when an autocalibration is desired, verify that the bin_search bit (register 1, bit 24) is set to 1. initiate the autocalibration process by toggling the en_autocal bit (register 1, bit 3) to 1. when the calibration is over, this bit is automatically reset to 0. during calibration, the rf local oscillator must be applied. at each clock cycle during an autocalibration sequence, the internal circuitry senses the output dc offset and calculates the new dc current for the dac. after the ninth clock cycle, the calibration is complete and the auto_cal bit is reset to 0. the dc offset dac state is stored in the internal registers and maintained as long as the power supply is kept on, or until the cal reset (register 1, bit 29) is toggled to 1 or a new calibration is started. the required clock speed for the optimum calibration is determined by the internal detector behavior (integration bandwidth, gain, sensitivity). the input bandwidth of the detector can be adjusted by changing the cutoff frequency of the rc low-pass filter in front of the detector (register 0, bits 24 ? 25), corresponding to 3-db corner-frequency steps of 10 mhz, 10 khz, and 1 khz. the speed of the clock can be slowed down by selecting a clock divider ratio (register 1, bits 25 ? 27). the detector has more averaging time the slower the clock; therefore, it can be desirable to slow down the clock speed for a given condition to achieve optimum results. for example, if there is no rf present on the rf input port, the detection filter can be left wide (10 mhz) and the clock divider can be left at div-by-1. the autocalibration yields a dc offset balance between the differential baseband output ports (i and q) that is less than 15 mv. some minor improvement may be obtained by increasing the averaging of the detector by increasing the clock divider up to 256. however, if there is a modulated rf signal present at the input port, it is desirable to reduce the detector bandwidth to filter out most of the modulated signal. the detector bandwidth can be set to a 1-khz corner frequency. with the modulated signal present, and with the detection bandwidth reduced, additional averaging is required to get optimum results. a clock divider setting of 1024 yields optimum results. an increase in the averaging is possible by increasing the clock divider at the expense of longer converging time. the convergence time can be calculated by the following: 18 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): trf3710 www.ti.com c ( auto_cal_clk_cycles ) ( clk_divider ) osc_freq
(2) alternate method for adjusting dc offset pcb layout guidelines trf3710 slws199a ? august 2007 ? revised february 2008 with a clock divider of 1024 and with the nominal oscillator frequency of 900 khz, the convergence time is: the internal registers controlling the internal dc current dac are accessible through the spi, providing a user-programmable method for implementing the dc offset calibration. to employ this option, the auto cal bit must be set to 0 and the bin_search set to 0. during this calibration, an external instrument monitors the output dc offset between the i/q differential outputs and programs the internal registers ( idac_bit[0:7] and qdac_bit[0:7] bits, register 1, bits 4 ? 19) to cancel the dc offset. the trf3710 also offers a third dc offset calibration option to control the output dc offset by an external voltage (0 ? 3 v) injected at the voffi and voffq pins. set pwd_dc_off_dig (register 0, bit 8) to 1 (off) and set pwd_dc_off_ana (register 0, bit 9) to 0 to engage the external analog voltage control of the output dc offset. the analog voltage at the voffi and voffq pins can be adjusted to provide the proper dc offset balance. the trf3710 device is designed with a ground slug on the back of the package that must be soldered to the printed-circuit board (pcb) ground with adequate ground vias to ensure a good thermal and electrical connection. the recommended via pattern and ground pad dimensions are shown in figure 34 . the recommended via diameter is 8 mils (0.203 mm). the ground pins of the device can be directly tied to the ground slug pad for a low-inductance path to ground. additional ground vias may be added if space allows. the nc (no connect) pins can also be tied to the ground plane. decoupling capacitors at each of the supply pins is recommended. the high-frequency decoupling capacitors for the rf mixers (vccmix) should be placed close to the respective pins. the value of the capacitor should be chosen to provide a low impedance rf path to ground at the frequency of operation. typically, this value is around 10 pf or lower. the other decoupling capacitors at the other supply pins should be kept as close to the respective pins as possible. the device exhibits symmetry with respect to the quadrature output paths. it is recommended that the pcb layout maintain that symmetry in order to ensure the quadrature balance of the device is not impaired. the i/q output traces should be routed as differential pairs and the lengths all kept equal to each other. decoupling capacitors for the supply pins should be kept symmetrical where possible. the rf differential input lines related to the rf input and the lo input should also be routed as differential lines with the respective lengths kept equal. if an rf balun is used to convert a single-ended input to a differential input, then the rf balun should be placed close to the device. implement the rf balun layout according to the manufacturer ? s guidelines to provide best gain and phase balance to the differential outputs. on the rf traces, maintain proper trace widths to keep the characteristic impedance of the rf traces at a nominal 50 ? . copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 19 product folder link(s): trf3710 www.ti.com c (9) (1024) 900 khz 10.24 ms
application schematics trf3710 slws199a ? august 2007 ? revised february 2008 figure 34. pcb layout guidelines the typical application schematic is shown in figure 35 . the rf bypass capacitors and coupling capacitors are depicted with 10-pf capacitors. these values can be adjusted to provide the best high-frequency bypass based on the frequency of operation. 20 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): trf3710 www.ti.com ? 0.008 (0,203) 0.025 (0,635) 0.200 (5,08) 0.200 (5,08) 0.0125 (0,318) dimensions: inches (mm) 0.025 (0,635)
adc interface trf3710 slws199a ? august 2007 ? revised february 2008 figure 35. trf3710 application schematic the rf input port and the rf lo port require differential input paths. single-ended rf inputs to these ports can be converted with an rf balun that is centered on the band of interest. linearity performance of the trf3710 depends on the amplitude and phase balance of the rf balun; therefore, care should be taken with the selection of the balun device and with the rf layout of the device. the recommended rf balun devices are listed in table 6 . table 6. recommended rf balun devices unbalance balance manufacturer part number frequency range (mhz) impedance impedance murata ldb211g8005c-001 1800 100 mhz 50 ? 50 ? murata ldb211g9005c-001 1900 100 mhz 50 ? 50 ? the trf3710 has an integrated adc driver buffer that allows direct connection to an analog-to-digital converter (adc) without additional active circuitry. the common-mode voltage generated by the adc can be directly supplied to the trf3710 through the vcmi/q pins (pins 24, 37). otherwise, a nominal common-mode voltage of 1.5 v should be applied to those pins. the trf3710 device can operate with a common-mode voltage from 1.5 v to 2.8 v without any impairment to the output performance. figure 36 illustrates the degradation of the output compression point as the common mode voltage exceeds those values. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 21 product folder link(s): trf3710 www.ti.com gnddig vccdig chip_en vccmix ncnc nc nc nc mixinpmixinn vccmix 1 2 3 4 5 6 7 8 9 10 11 12 25 26 27 28 29 30 31 32 33 34 35 36 vccbbi adc_cm( 1.5v) ~ adc_cm( 1.5v) ~ c1 0.1 f m c11 0.1 f m c12 0.1 f m c2 c8 c3 c6 1000 pf 1000 pf 10 pf 10 pf 10 pf 10 pf 10 pf 0.1 f m agnd bbioutp bbioutn loip loin nc bbqoutp bbqoutn agnd vccbbq vcclo vcc vcc vcc vcc vcc bbin bbqn lon 13 14 15 16 17 18 19 20 21 22 23 24 37 38 39 40 41 42 43 44 45 46 47 48 ncnc nc mixqoutp mixqoutn nc nc rextvccbias gndbias voffq vcmq sclk sdat strobe mixioutp mixioutn ncnc gain_b0 gain_b1gain_b2 voffi vcmi u1 trf3710 rf in r1 30 k w to adc q to synthesizer clock da ta strobe gain_b0 gain_b1 gain_b2 to adc i bbip bbqp lop c10 vcc vcc chip_en 10 pf c9 c5 ldb21 c4 c7 b1
application for a high-performance rf receiver signal chain trf3710 slws199a ? august 2007 ? revised february 2008 figure 36. p1db performance vs common-mode voltage the trf3710 is the centerpiece component in a high-performance direct downconverting receiver. the device is a highly integrated direct downconverting demodulator that requires minimal additional devices to complete the signal chain. a signal chain block diagram example is shown in figure 37 . figure 37. block diagram of direct downconverting receiver the lineup requires a low-noise amplifier (lna) that operates at the frequency of interest with typical 1-db to 2-db noise-figure (nf) performance. an rf band-pass filter (bpf) is selected at the frequency band of interest to eliminate unwanted signals and images outside the band from reaching the demodulator. the trf3710 incorporates the direct downconverter demodulation, baseband filtering, and baseband gain control functions. an external synthesizer, such as the trf3761 , provides the local oscillator (lo) source to the trf3710. the differential outputs of the trf3761 directly mate with the lo inputs of the trf3710. the quadrature outputs (i/q) of the trf3710 directly drive the input to the adc. a dual adc such as the ads5232 12-bit, 65-msps adc mates perfectly with the differential i/q output of the trf3710. in addition, the common-mode output voltage generated by the ads5232 is fed directly into the common-mode ports (pins 24, 37) to ensure the optimum dynamic range of the adc is maintained. 22 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): trf3710 www.ti.com 0 0.5 1 1.5 2 2.5 3 3.5 0.5 1 1.5 2 2.5 3 3.5 v C common-mode voltage C v cm p1db C dbv rms 0 90 trf371x lna trf3761 ads5232 12 12
trf3710 slws199a ? august 2007 ? revised february 2008 the cascaded performance of the trf3710 with the ads5232 and the trf3761 was measured with wcdma modulated signals. a single channel wcdma receive signal was injected into the trf3710 at ? 100 dbm. this power roughly corresponds to typical levels this device would see at sensitivity when an appropriate lna and filter are used. the error-vector magnitude (evm) of the rx channel was measured as a gauge of the system performance. the evm percentage at ? 100 dbm is approximately 27.6% at 60 ksym/s. this result correlates with the required signal-to-noise ratio (snr) for the device with an appropriate lna to meet or exceed the bit error rate (ber) specification of 0.1% according to the standards at the input sensitivity level. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 23 product folder link(s): trf3710 www.ti.com
package option addendum www.ti.com 10-jun-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples trf3710irgzr active vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 trf 3710 trf3710irgzt active vqfn rgz 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 trf 3710 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 10-jun-2014 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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